1. Field of the Invention
Methods and apparatuses consistent with the present invention relate to reading memory data. More particularly, methods and apparatuses consistent with the present invention relate to reading memory data which can rapidly read multi-bit information stored in memory cells consisting of a flash memory.
2. Description of Related Art
Currently, demands for a large-volume memory have been exponentially increased, and accordingly, recent research relating to the large-volume memory has been actively undertaken. Particularly, demands for a flash memory capable of reducing power consumption and maintaining stored data without power supply have been increased every year.
Flash memory advantageously maintains stored data without power supply in comparison with a related art DRAM, and allows data to be electrically inputted/outputted, and thus, a range of applications for the flash memory is greatly expanded. Hereinafter, the flash memory and the related arts will be described.
The flash memory is mainly classified into a NAND flash memory which is useful in a large-scale integration and provides a large storage volume, and a NOR flash memory which has a relatively fast read speed. The NAND flash memory lags the NOR flash memory in the read speed, but can be implemented by highly integrating the memory cell. Particularly, modern day NAND flash memory devices electrically program and erase memory cells to store and maintain data.
Generally, the flash memory includes a plurality of memory cells. The memory cell can be implemented by using a transistor. Also, the transistor includes a drain, a source, a gate, and a floating gate. Generally, in the DRAM, electrons are stored in a capacitor, and the stored electrons in the capacitor are detected and thereby allow data stored in the DRAM to be detected. Unlike this, a method of storing data in the memory cell including the transistor is performed such that a threshold voltage of the transistor is changed by charging electric stimulation to the memory cell from the outside.
For example, when a positive high voltage is applied to a gate of the transistor, electrons are accumulated in the floating gate by Fowler-Nordheim tunneling effect. As electrons are accumulated in the floating gate, the threshold voltage of the transistor is increased. Conversely, as the accumulated electrons in the floating gate are discharged, the threshold voltage of the transistor is reduced. According to a principle of the change of the threshold voltage, data is stored in the memory cell and detected.
Two methods of storing data in the flash memory have been mainly proposed. Of these, a Single Level Cell (SLC) method is conducted such that threshold voltages of transistors are determined into one threshold voltage. As for the SLC method, when a predetermined voltage is applied to a gate of the transistor, data stored in the memory cell is detected depending on whether the transistor is either ON or OFF.
As demands for the large volume flash memory are currently increasing, a Multi Level Cell (MLC) method draws attention. The MLC method is to multiplex the threshold voltage of the transistor included in the memory cell. For example, when 4-bit data is stored, the threshold voltage of the transistor is set into 16 levels, and data is then assigned in accordance with each level. Thus, the MLC method surpasses SLC method in storing large-volume data.
For example, the threshold voltage of the transistor theoretically has 16 values in the memory cell in which 4-bit data is stored and the MLC method is adapted. However, realistically, the threshold voltage does not exactly have 16 values, and is separated into 16 regions and distributed. Further, corresponding data is stored in each region of 16 regions. To read data stored in the memory cell by the MLC method, a data value which is stored in the memory cell with respect to each region of 16 regions is required to be determined. Thus, to read data stored in a 4-bit memory cell, 15 gate voltages should be sequentially applied.
In particular, the NAND flash memory includes a memory cell array. The memory cell array is formed by arranging a plurality of memory cells in transversal and longitudinal directions. Generally, a plurality of bit lines are used to connect memory cells on transversal rows and a plurality of word lines are used to connect memory cells on longitudinal columns.
For example, we assume that a number of word lines is N, that is, WL1, WL2, . . . , WLN. Since, it is unknown which region each threshold voltage of memory cells connected with word lines is included, every region in which threshold voltages are included should be determined. Specifically, when 4-bit data is stored in the memory cell, reading should be performed while word line voltages of WLN is being changed 15 times. As a result, the flash memory of the MLC method has a shortcoming in which a read speed is relatively low.
Therefore, there is a need for apparatuses and methods for reading memory data in which the read speed is increased while taking advantage of the MLC method.